Overview‍

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Join Microsoft Research Cambridge to design analogue integrated CMOS circuits for the Analogue Optical Computer, advancing low power AI hardware with a multidisciplinary research team.

The position is based at Microsoft Research Cambridge within the Future AI Infrastructure group. The lab conducts world-leading research that has influenced many of Microsoft’s products and partnerships. The group is highly cross-disciplinary, spanning circuits, optics, computer science and engineering, and works closely with product teams and academic partners to tackle the challenges of next generation cloud infrastructure.

The role focuses on translating early analogue compute concepts into silicon, developing fast and low energy CMOS building blocks and working closely with collaborators across the AOC project, including algorithm, digital twin, and optical system development. You will contribute to an ambitious effort to create novel hardware that improves the performance and efficiency of large-scale AI workloads.

Contract Length: 2 Years

Location: Cambridge, UK

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‍Responsibilities‍

You will advance analogue compute research by taking new circuit concepts through simulation, layout, and silicon validation, creating CMOS blocks optimised for speed and energy.

• Research, develop, and implement analogue and mixed signal CMOS circuits such as nonlinear functions, amplifiers, and sample and hold elements.

• Perform transistor level analysis, simulation, and optimisation.

• Produce layouts in a 180 nm process and prepare designs for MPW fabrication.

• Build and evaluate research prototypes, troubleshooting issues from schematic to silicon.

• Explore scaling paths to advanced nodes and assess architectural and topological trade-offs.

• Work closely with collaborators on algorithms, digital twin modelling, and optical system integration.

• Communicate results clearly, sharing insights with the wider AOC team and partner groups.

• Contribute to an open, multidisciplinary research environment.

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‍Qualifications‍

Required/Minimum Qualifications:  

• PhD (or close to completion) in Electrical Engineering or a related discipline, or equivalent experience in analogue IC design.

• Strong understanding and hands-on experience with analogue CMOS circuit design, including transistor-level design, simulation, and layout.

• Proficiency with Cadence EDA design tools.

• Experience taking designs through to tape-out.

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Preferred/Additional Qualifications:

• Experience with 180nm CMOS nodes and below

• Knowledge of low power and broadband high speed design techniques, including optimisation of trade-offs between speed, accuracy, noise, and energy.

• Familiarity with analogue signal processing circuits and nonlinear analogue circuit design.

• Experience with physical measurement, characterisation, or testing of analogue circuits.

• Interest or experience in working with non-traditional or experimental hardware in a research environment.

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This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

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