AWS Utility Computing (UC) provides product innovations — from foundational services such as Amazon’s Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS’s services and features apart in the industry. As a member of the UC organization, you’ll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, Amazon Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Join a groundbreaking semiconductor team where your expertise will directly power the world's largest cloud infrastructure. At Annapurna Labs, you'll be instrumental in developing next-generation chip technologies that transform how global businesses leverage computing power, working at the intersection of innovative design and cutting-edge technological advancement.
Watch these videos to learn more about Annapurna Labs and the Nitro project:
AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 - Deep Dive into the AWS Nitro System https://www.youtube.com/watch?v=cD1mNQ9YbeA
* Develop comprehensive Design-for-Testability (DFT) strategies for next-generation semiconductor platforms
* Collaborate across multiple engineering domains to ensure robust chip design and verification
* Generate and optimize test patterns using advanced methodological approaches
* Conduct detailed logic design and verification processes
* Support chip bring-up and contribute to the entire device lifecycle from definition to mass production
- Bachelor's degree in Computer/Electrical Engineering. Make sure to include a grade sheet with your CV in a single PDF.
- Knowledge of chip design principles
- Experience with Verilog and System Verilog
- Experience with verification methodologies
- Familiarity with ATPG and scan insertion tools
- Scripting skills in Perl/Tcl
- Understanding of gate-level simulations and static timing analysis
