You will:

• Work closely with the design team to define specifications and test plans
• Execute on test plans, including test development, reference model design, and failure debug. Verify key functionality and performance use cases.
• Contribute to the development of overall verification infrastructure, tools, and methodology
• Identify and integrate third-party verification IP
• Collect and analyze coverage metrics
• Advocate and establish verification best-practices

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You have:

• 3+ years of experience using UVM to verify ASICs
• Knowledge of SystemVerilog
• Experience with digital architecture and logic
• Advanced verification techniques like constrained random generation, functional coverage, and assertions

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We prefer:

• Experience with the full digital design verification cycle -- from spec through bring-up
• Experience with performance and power validation, digital design (RTL), and formal verification
• Experience with machine learning and other high performance compute elements
• Experience with C/C++ for reference model development and enhancement
• Familiarity with formal verification methods
• Experience with industry standard protocols, interfaces, and IP components, such as PCIe, DDR, Ethernet, and NoCs

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