Description
In this role, you will learn the fundamentals of chip-level integration and support the development of our world-class SoCs. You will assist senior engineers with top-level design tasks and gain hands-on experience with front-end (FE) design flows for RTL and Netlist. You will work closely with and learn from our architecture, verification, CAD, and physical design teams, helping to support various design methodologies and contributing to successful project execution.
Minimum Qualifications
- 2+ years of relevant experience in chip design, including internships or significant academic projects
- Familiarity with chip design principles and front-end (FE) design tools (e.g., Lint, Synthesis, Logic Equivalence)
- Coursework or project experience related to Clock/Reset Domain Crossing (CDC/RDC) verification is a plus
- An understanding of digital design, hierarchical design approaches, and top-down design
- Basic scripting skills (e.g., Python, Perl, Tcl) are highly desirable
- Comfortable leveraging AI/LLM tools to enhance productivity, such as for script generation, code analysis, or accelerating learning
- Excellent communication skills and a strong desire to work in a collaborative team environment
- A strong aptitude and enthusiasm for learning new tools, flows, and methodologies
Preferred Qualifications
- BSc or MSc in Electrical Engineering or Computer Engineering.
