RESPONSIBILITIES:

• Responsible for digital ASIC verification at block and system level
• Write and review test plans, develop test harnesses and test sequences
• Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs
• Responsible for test plan execution, running regressions, code and functional coverage closure
• Automate test case generation by using Python and MATLAB programs
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

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BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer science or computer engineering
• 2+ years of experience with design verification and test bench development

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PREFERRED SKILLS AND EXPERIENCE:

• Advanced degree in electrical engineering or computer engineering
• Experience with verification methodologies such as UVM
• Strong object-oriented programming knowledge
• Strong problem-solving and coding skills
• Experience in constrained random verification
• Expertise in developing test plans, implementing coverage models, and analyzing results
• Experience with scripting languages, e.g. Python for automation
• RTL design, chip bring-up, and post-silicon validation experience
• Ability to work in a dynamic environment with changing needs and requirements

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ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

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