We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

‍

‍

What you'll be doing:

• Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
• Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
• Work in a cross-functional environment interacting with multiple teams.
• Apply knowledge and experience to improve timing convergence flows working with the methodology teams.

‍

‍

What we need to see:

• BS (or equivalent experience) or MS (preferred) in Electrical or Computer Engineering with 2 years’ experience
• Experience with Static Timing Analysis (STA)
• Experience physical design and optimization e.g., synthesis, floorplanning, placement, CTS, routing, power, etc. is a plus
• Hands-on experience with industry standard EDA tools.

‍

‍

Ways to stand out from the crowd:

• Industry experience in timing convergence for ASICs, CPUs, GPUs or Network processors.
• Knowledge of deep sub-micron process nodes.
• Proficiency in AI/LLM and programming languages.

‍