MMPLEX is NVIDIA's multi-media team. It covers several different directions including Display/Video/Security/Accelerators. Our ASIC role is responsible for RTL design and all other related front-end flow.

What you’ll be doing:

• Micro architecture design.
• RTL (Verilog) coding.
• Design implementation using Synopsys/Cadence tools.
• Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction)
• Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off.  (PD Direction)
• Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction)
• FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction)
• Methodology in any of above areas.

What we need to see:

• MS degree from EE/CS or related majors from a prestigious university.
• Good knowledge in digital circuit design.
• Experience in using Verilog HDL.
• Experience in various of ASIC EDA tools.
• Fluent in English reading and writing.
• Self-motivated, good team player.

Ways to stand out from the crowd:

• Proven ability to work independently as well as in a multi-disciplinary group environment
• Good command of C/C++ programming language.
• Hand-on experience in any related area is a plus.